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? semiconductor components industries, llc, 2013 october, 2013 ? rev. 0 1 publication order number: ntlld4951nf/d ntlld4951nf dual n-channel power mosfet with integrated schottky 30 v, high side 11 a / low side 13 a, dual n ? channel, wdfn (3 mm x 3 mm) features ? co ? packaged power stage solution to minimize board space ? low side mosfet with integrated schottky ? minimized parasitic inductances ? optimized devices to reduce power losses ? these devices are pb ? free, halogen free/bfr free and are rohs compliant applications ? dc ? dc converters ? system voltage rails ? point of load wdfn8 case 511bp marking diagram http://onsemi.com v (br)dss r ds(on) max i d max q1 top fet 30 v 17.4 m @ 10 v 11 a 25 m @ 4.5 v (8) g2 s2 (5, 6, 7) q2 bottom fet 30 v 13.3 m @ 10 v 13 a 20 m @ 4.5 v (1) g1 s1/d2 (10) d1 (2, 3, 4, 9) 1 4951 = specific device code a = assembly location y = year ww = work week = pb ? free package 4951 ayww 1 (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information 10 9 1 2 3 4 8 7 6 5 pin connections d1 s1/d2 g1 d1 d1 d1 g2 s2 s2 s2 (bottom view)
ntlld4951nf http://onsemi.com 2 maximum ratings (t j = 25 c unless otherwise stated) parameter symbol value unit drain ? to ? source voltage q1 v dss 30 v drain ? to ? source voltage q2 gate ? to ? source voltage q1 v gs 20 v gate ? to ? source voltage q2 continuous drain current r ja (note 1) steady state t a = 25 c q1 i d 8.3 a t a = 85 c 6.0 t a = 25 c q2 9.6 t a = 85 c 6.9 power dissipation r ja (note 1) t a = 25 c q1 p d 1.82 w q2 1.88 continuous drain current r ja 10 s (note 1) t a = 25 c q1 i d 11 a t a = 85 c 8 t a = 25 c q2 13 t a = 85 c 9.1 power dissipation r ja 10 s (note 1) t a = 25 c q1 p d 3.23 w q2 3.27 continuous drain current r ja (note 2) t a = 25 c q1 i d 5.5 a t a = 85 c 4.0 t a = 25 c q2 6.3 t a = 85 c 4.5 power dissipation r ja (note 2) t a = 25 c q1 p d 0.80 w q2 0.81 pulsed drain current ta = 25 c tp = 10 s q1 i dm 65 a q2 70 operating junction and storage temperature q1 t j , t stg ? 55 to +150 c q2 source current (body diode) q1 i s 4.2 a q2 6.0 drain to source dv/dt dv/dt 6 v/ns single pulse drain ? to ? source avalanche energy (t j = 25c, v dd = 50 v, v gs = 10 v, i l = 9.0 a pk , l = 0.3 mh, r g = 25 ) q1 eas 12 mj single pulse drain ? to ? source avalanche energy (t j = 25c, v dd = 50 v, v gs = 10 v, i l = 9.5 a pk , l = 0.3 mh, r g = 25 ) q2 eas 13.5 lead temperature for soldering purposes (1/8? from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. surface ? mounted on fr4 board using 1 sq ? in pad, 2 oz cu 2. surface ? mounted on fr4 board using the minimum recommended pad size of 90 mm 2
ntlld4951nf http://onsemi.com 3 thermal resistance maximum ratings parameter fet symbol value unit junction ? to ? ambient ? steady state (note 3) q1 r ja 68.8 c/w q2 66.4 junction ? to ? ambient ? steady state (note 4) q1 r ja 156.4 q2 153.9 junction ? to ? ambient ? (t 10 s) (note 3) q1 r ja 38.7 q2 38.2 3. surface ? mounted on fr4 board using 1 sq ? in pad, 2 oz cu 4. surface ? mounted on fr4 board using the minimum recommended pad size of 90 mm 2 electrical characteristics (t j = 25 c unless otherwise specified) parameter fet symbol test condition min typ max unit off characteristics drain ? to ? source break- down voltage q1 v (br)dss v gs = 0 v, i d = 250 a 30 v q2 30 drain ? to ? source break- down voltage temperature coefficient q1 v (br)dss / t j 18 mv / c q2 15 zero gate voltage drain current q1 i dss v gs = 0 v, v ds = 24 v t j = 25 c 1 a t j = 125 c 10 q2 v gs = 0 v, v ds = 24 v t j = 25 c 500 gate ? to ? source leakage current q1 i gss v gs = 0 v, vds = 20 v 100 na q2 100 on characteristics (note 5) gate threshold voltage q1 v gs(th) v gs = vds, i d = 250 a 1.2 2.2 v q2 1.2 2.2 negative threshold temper- ature coefficient q1 v gs(th) / t j 4.5 mv / c q2 4.0 drain ? to ? source on resist- ance q1 r ds(on) v gs = 10 v i d = 9 a 14 17.4 m v gs = 4.5 v i d = 9 a 20 25 q2 v gs = 10 v i d = 11 a 11 13.3 v gs = 4.5 v i d = 11 a 16 20 forward transconductance q1 g fs v ds = 1.5 v, i d = 9 a 16 s q2 18 charges, capacitances & gate resistance input capacitance q1 c iss v gs = 0 v, f = 1 mhz, v ds = 15 v 605 pf q2 660 output capacitance q1 c oss 190 q2 325 reverse capacitance q1 c rss 102 q2 17.5 5. pulse test: pulse width 300 s, duty cycle 2% 6. switching characteristics are independent of operating junction temperatures.
ntlld4951nf http://onsemi.com 4 electrical characteristics (t j = 25 c unless otherwise specified) parameter unit max typ min test condition symbol fet charges, capacitances & gate resistance total gate charge q1 q g(tot) v gs = 4.5 v, v ds = 15 v; i d = 9 a 6.5 nc q2 5.0 threshold gate charge q1 q g(th) 1.1 q2 1.1 gate ? to ? source charge q1 q gs 1.9 q2 2.0 gate ? to ? drain charge q1 q gd 3.2 q2 1.46 total gate charge q1 q g(tot) v gs = 10 v, v ds = 15 v; i d = 9 a 12 nc q2 10.6 switching characteristics (note 6) turn ? on delay time q1 t d(on) v gs = 4.5 v, v ds = 15 v, i d = 9 a, r g = 3.0 8.0 ns q2 7.5 rise time q1 t r 7.2 q2 11.2 turn ? off delay time q1 t d(off) 11 q2 11.6 fall time q1 t f 3.3 q2 1.9 switching characteristics (note 6) turn ? on delay time q1 t d(on) v gs = 10 v, v ds = 15 v, i d = 9 a, r g = 3.0 4.2 ns q2 4.3 rise time q1 t r 11.6 q2 11.4 turn ? off delay time q1 t d(off) 14.1 q2 14.3 fall time q1 t f 2.0 q2 1.3 drain ? source diode characteristics forward voltage q1 v sd v gs = 0 v, i s = 3 a t j = 25 c 0.80 1.2 v t j = 125 c 0.65 q2 v gs = 0 v, i s = 2 a t j = 25 c 0.50 0.80 t j = 125 c 0.45 5. pulse test: pulse width 300 s, duty cycle 2% 6. switching characteristics are independent of operating junction temperatures.
ntlld4951nf http://onsemi.com 5 electrical characteristics (t j = 25 c unless otherwise specified) parameter unit max typ min test condition symbol fet drain ? source diode characteristics reverse recovery time q1 t rr v gs = 0 v, d is /d t = 100 a/ s, i s = 3 a 17.9 ns q2 23.3 charge time q1 ta 9.0 q2 11.3 discharge time q1 tb 9.0 q2 12 reverse recovery charge q1 q rr 8.0 nc q2 12 package parasitic values source inductance q1 l s t a = 25 c 0.36 nh q2 0.36 drain inductance q1 l d 0.054 nh q2 0.054 gate inductance q1 l g 1.3 nh q2 1.3 gate resistance q1 r g 0.8 q2 0.8 5. pulse test: pulse width 300 s, duty cycle 2% 6. switching characteristics are independent of operating junction temperatures. ordering information device package shipping ? NTLLD4951NFTWG wdfn8 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ntlld4951nf http://onsemi.com 6 typical characteristics ? q1 figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 5 4 3 2 1 0 0 10 20 25 5 4.0 3.0 2.0 1.5 1.0 0 5 10 25 figure 3. on ? resistance vs. gate ? to ? source resistance figure 4. on ? resistance vs. drain current and gate voltage v gs , gate ? to ? source voltage (v) i d , drain current (a) 9 810 7 6 5 4 2 10 20 25 30 40 45 55 30 25 20 10 5 0 13 14 15 17 20 22 23 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source voltage (v) 125 100 75 50 25 0 ? 25 ? 50 0.5 1.2 1.4 1.6 1.7 30 25 20 15 10 0 1e ? 11 1e ? 10 i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance (m ) r ds(on) , drain ? to ? source resistance (m ) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (a) 15 v gs = 2.2 v 3.0 v 3.2 v 2.8 v 7.5 v 10 v t j = 25 c v ds = 5 v t j = 125 c t j = ? 55 c 15 20 15 35 50 i d = 10 a 15 19 t = 25 c v gs = 4.5 v v gs = 10 v 150 i d = 9 a v gs = 10 v 0.8 1.0 t j = 125 c t j = 150 c 3 5 3.4 v 3.6 v 3.8 v 2.6 v 2.4 v 4.5 v thru 4 v 2.5 3.5 30 16 18 21 1.1 1.3 1.5 0.7 0.9 0.6 t j = 25 c 1e ? 09 1e ? 08 1e ? 07 1e ? 06 1e ? 05
ntlld4951nf http://onsemi.com 7 typical characteristics ? q1 figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) qg, total gate charge (nc) 30 25 20 15 10 5 0 0 100 200 400 500 600 700 800 12 6 4 2 0 0 1 3 5 6 8 9 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 1 10 100 0.9 0.8 0 0.7 0.6 0.5 0.4 0.3 0 1 2 3 4 5 6 c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) 300 t j = 25 c v gs = 0 v c iss c oss c rss 810 2 4 7 10 i d = 9 a t j = 25 c v gs = 4.5 v v dd = 15 v qt qgs qgd v gs = 10 v v dd = 15 v i d = 10 a t d(off) t d(on) t f t r t j = 25 c v gs = 0 v 7 8 9 0.1 0.2 0.01 0.1 1 10 100 0.1 1 10 100 figure 11. maximum rated forward biased safe operating area v ds , drain ? to ? source voltage (v) i d , drain current (a) r ds(on) limit thermal limit package limit v gs = 20 v single pulse t c = 25 c 1 ms 10 s 10 ms dc 100 s 1.0 1.1 figure 12. maximum avalanche energy vs. starting junction temperature t j , starting junction temperature ( c) 130 115 25 100 85 70 55 0 2 4 6 8 10 e as , single pulse drain ? to ? source avalanche energy (mj) i d = 9 a 12 14 40 145 160
ntlld4951nf http://onsemi.com 8 typical characteristics ? q1 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 0.1 0.2 0.02 d = 0.5 0.05 0.01 single pulse thermal resistance, r ja(t) ( c/w) t, pulse time (sec) figure 13. thermal response
ntlld4951nf http://onsemi.com 9 typical characteristics ? q2 figure 14. on ? region characteristics figure 15. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 5 4 3 2 1 0 0 10 20 25 5 30 3.5 3 2 1 0 10 15 30 40 figure 16. on ? resistance vs. gate ? to ? source resistance figure 17. on ? resistance vs. drain current and gate voltage v gs , gate ? to ? source voltage (v) i d , drain current (a) 9 810 7 6 5 4 2 0 30 40 60 30 25 20 10 5 0 8 10 12 14 18 20 figure 18. on ? resistance variation with temperature figure 19. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source voltage (v) 125 100 75 50 25 0 ? 25 ? 50 0.6 1.2 1.4 1.6 30 25 20 15 10 0 1e ? 06 1e ? 05 1e ? 04 1e ? 02 i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance (m ) r ds(on) , drain ? to ? source resistance (m ) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (a) 15 35 40 v gs = 2.2 v 3.0 v 2.8 v 7.5 v 10 v t j = 25 c v ds = 5 v t j = 125 c t j = ? 55 c 20 25 10 i d = 10 a 15 40 35 16 v gs = 4.5 v v gs = 10 v 150 i d = 11 a v gs = 10 v 0.8 1.0 v gs = 0 v t j = 125 c t j = 150 c 3 5 3.2 v 3.4 v 2.5 1.5 1e ? 03 t j = 25 c 2.6 v 2.4 v 3.6 v 3.8 v 4.5 thru 4.0 v 5 35 20 50 4.5 4 t = 25 c
ntlld4951nf http://onsemi.com 10 typical characteristics ? q2 figure 20. capacitance variation figure 21. gate ? to ? source and drain ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) qg, total gate charge (nc) 30 25 20 15 10 5 0 1 100 1000 6 4 2 0 0 1 3 5 6 8 9 figure 22. resistive switching time variation vs. gate resistance figure 23. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 1 10 100 0.9 0.8 0 0.7 0.6 0.5 0.4 0.3 0 1 2 3 4 5 6 c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) 10 t j = 25 c v gs = 0 v c iss c oss c rss 810 2 4 7 10 i d = 9 a t j = 25 c v gs = 4.5 v v dd = 15 v qt qgs qgd v gs = 10 v v dd = 15 v i d = 10 a t d(off) t d(on) t f t r t j = 25 c v gs = 0 v 7 8 0.1 0.2 0.01 0.1 1 10 100 0.1 1 10 100 figure 24. maximum rated forward biased safe operating area v ds , drain ? to ? source voltage (v) i d , drain current (a) r ds(on) limit thermal limit package limit 0 v < v gs < 20 v single pulse t c = 25 c 1 ms 10 s 10 ms dc 100 s 1.0 figure 25. maximum avalanche energy vs. starting junction temperature t j , starting junction temperature ( c) 130 115 25 100 85 70 55 0 2 4 6 8 10 e as , single pulse drain ? to ? source avalanche energy (mj) i d = 9.5 a 12 14 40 145 160
ntlld4951nf http://onsemi.com 11 typical characteristics ? q2 0.01 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 0.1 0.2 0.02 d = 0.5 0.05 0.01 single pulse thermal resistance, r ja(t) ( c/w) t, pulse time (sec) figure 26. thermal response
ntlld4951nf http://onsemi.com 12 package dimensions wdfn8 3x3, 0.65p case 511bp issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.05 and 0.15 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. 5. positional tolerance applies to all of the exposed pads. ??? ??? ??? ??? a d e b c 0.15 pin one reference top view side view bottom view k d2 e2 c c 0.15 c 0.10 c 0.08 a1 seating plane note 3 b 8x 0.10 c 0.05 c a b dim min max millimeters a 0.70 0.80 a1 0.00 0.05 b 0.30 0.50 d 3.00 bsc d2 2.35 2.55 e 3.00 bsc e2 0.90 1.10 e 0.65 bsc l 0.20 0.40 1 4 8 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.65 pitch 1.15 3.30 1 dimensions: millimeters 0.43 note 4 0.50 5x detail a a3 0.20 ref a3 a detail b l1 detail a l alternate constructions ?? ??? ??? 0.00 0.15 e recommended g 0.43 bsc 5 2.60 e3 0.40 0.60 g2 0.68 bsc k 0.20 ??? e/2 e3 g g2 a m 0.10 b c m m a m 0.10 b c note 5 note 5 1.80 0.50 6x 0.68 0.65 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ntlld4951nf/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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